This invention relates generally to semiconductor devices and integrated circuits and more particularly to such devices and circuits utilizing a polysilicon material in place of other known materials.
The development of large scale integrated circuits (LSI) has been one of the major steps forward in the semiconductor circuit art. This improvement brought to the forefront new techniques which allow many circuits to be constructed on a single clip. These technologies have appropriately derived acrynoms allowing those skilled in the art to readily understand the construction and operation of the device and in some instances the circuit.
By way of example, these acrynoms which are of interest to this invention include MOS (metal oxide semiconductor), JFET (junction field effect transistors), and the MESFET (metal silicon field effect transistor) perhaps more appropriately termed a Schottky junction field effect transistor.
The technology that developed MOS integrated circuits and LSI's has adopted polycrystalline silicon ("polysilicon") as an effective material for use, as a mechanical support, as resistive or field shaping layers and as the conductor over the gate insulator in MOS devices. However, for a number of reasons polysilicon has never been thought to be practical in the technology that accompanied the JFET or MESFET.
The JFET has not been compatible with the LSI art because the conventional JFET is difficult to utilize for fabricating high density circuits necessary for implementing LSI technology techniques. This is partially because of biasing difficulties when conventional p-n junction isolation techniques are used. Also the connectivity, the art of connecting transistor components in an LSI is more difficult for conventional JFET's because of the length of the metal contacts and the multi-level metalization required. Further the JFET gate metal must be placed precisely over the gate p-n junction which limits manufacturing very small high density JFET devices required for LSI.
If the JFET is used for making LSI in unconventional dielectrically isolated structures such as silicon on sapphire (SOS), so that p-n junction isolation is not required, problems occur because of the thickness of the silicon in the (SOS) structure that is required for forming the gate p-n junction and allowing for the depletion region extension. This thickness problem also does not allow conventional JFET structure to be fabricated on the same chip as MOS structures not being fabricated in SOS structures.
Because of its nature and theory of operation, the JFET has been shown to be an effective device for evaluating the silicon sapphire interface to predict the radiation induced leakage current effects that would occur for MOS/LSI made in SOS structures. However the thickness requirement of the silicon substrate presently restricts conventional JFET test structures from being fabricated in real MOS/LSI structures.